Design Problem: Using the IBM $0\mathrm{.}18$um CMOS $($cmrf$7$sf$)$ process, design a

$$Ring Oscillator$$ using odd number $($N$)$ of CMOS inverter stages connected

in a circular chain that meets the following requirements:

a$)$ Frequency of oscillation $1$GHz within a margin of $100$MHz$.$

b$)$ Design parameters to consider: N$,$ W n $($NMOS transistor width$),$ W p

$($PMOS transistor width$).$

c$)$ DC Supply voltage to CMOS inverter do not exceed $1\mathrm{.}8$V$.$

d$)$ Verify and optimize the design using Cadence simulator showing

output oscillating voltage waveform. Compute the frequency of

oscillation. Using Cadence Virtuoso layout tool, generate the basic

layout of the Ring Oscillator designed, run DRC$/$LVS and attach

DRC$/$LVS output log