Design the following system:

$1-8$ sources $(8$ bits each$).$

$2-2$ destination registers

$3-$ Select $2$ source registers $($for example $1$ and $5)$

$4-$ Sources Register S$1$ should be loaded to destination reg. D$1$

$5-$ Sources Register S$2$ should be loaded to destination reg. D$2$

Scenario $1$: S$1$ sends to D$1$ and S$2$ sends to D$2$ during same clock period

Scenario $2$: S$1$ sends to D$1$ and S$2$ sends to D$2$ on two clock periods

$6-$ Draw the logic diagram