detail solution required urgently

Do D, D D (4) (5) (6) (1) (9) (10) CTR DIV 16 (15) (b) Draw the timing diagram for the IC in Figure-1. The CLR inputs are shown in LOAD Figure-2 and data inputs (DO, D1, D2, ENP and D3) are 1101 respectively. (9+6) TC = 15 RCO (2) CLK PC (14)|(13)|(12)|(11 2. O, O, O Data outputs Figure-1 Page 2 of 2 LOAD Figure-2