Determine which lines have syntax errors in the (Note selecting wrong answers would cause a penalty) accompanying VHDL code: 1 Tibrary ieee; 2 use ieee.stdiogic_1164.all: 3 Bentity Error_Finder is generic 5 (NUML STAGES : natural := 16): port ( clk, enable, reset, sr_in: std_logic; sr_out : out std_logic;); 9 end entity: 10 Earchitecture rtl of Error_finder is 11 type r_length is array ((NUM STAGES-1) to 0) of std_logic; 12 signal sr: sr_length: 13 abegin process (clk, reset) 15 begin 16 if (reset = '1') then 17 sr '0') : 18 elsif Srising_edge (clk)) then 19 if enable = '1') then 20 sr((NUM_STAGES-1) downto 1)