Develop a Reduced Instruction Set Computer to be implemented in the FPGA.

Develop each box in the diagram as a block or module

Your controller will have $16-$bit IR value and RF$\_$Rp$\_$zero as inputs; Identify your outputs for each opcode $($left most $4-$bits in the instruction$)$

Design a four steps execute process per instruction

Fetch $($instruction at memory location PC into IR$)$

Decode

Execute

Update PC $($to the next memory location$)$

Instructions to be demonstrated:

LW $52011001\_0101\_1100\_1001$

LW $62021001\_0110\_1100\_1010$

ADD $7560000\_0111\_0101\_0110$

SW $72031010\_0111\_1100\_1011$

LI $82501000\_1000\_1111\_1010$

SUB $4850001\_0100\_1000\_0101$

SW $42041010\_0100\_1100\_1100$

SRA $370110\_0010\_0111\_0000$

XOR $2340100\_0010\_0011\_0100$

SW $22051010\_0010\_1100\_1101$

Store suitable initial values at memory locations $201$ and $202$

Output: Show the values in memory locations $203,204$ and $205$ in $7-$segment display once all instructions are executed.

The report should include the cover page, the problem statement, explanation of your approach including the reuse of previously developed modules, a block diagram, ASM$-$D charts, Verilog codes used, the waveform screen$-$prints, one photos of the synthesis on the board.

State problems encountered at simulation and synthesize how they were resolved.