Devise a test of follwing "Add Shift Multiply" algorithms, Provide a table output of the algorithm and Supply waveform snapshots that show the process and the answer

Verilog code:

$//$behavioral add$-$shift multiply

module mul$\_$add$\_$shift$3($a$,$ b$,$ prod, start$)$;

input $[3$:$0]$ a$,$ b;

input start;

output $[7$:$0]$ prod;

reg $[7$:$0]$ prod;

reg $[3$:$0]$ b$\_$reg;

reg $[3$:$0]$ count;

always @ $($posedge start$)$

begin

b$\_$reg $=$ b;

prod $=0$;

count $=4\text{'}$b$0100$;

if $(($a$!=0)$ && $($b$!=0))$

while $($count$)$

begin

prod $=\{((\{4\{$b$\_$reg$[0]\}\}$ & a$)$

$+$ prod$[7$:$4]),$ prod$[3$:$1]\}$;

b$\_$reg $=$ b$\_$reg $>>1$;

count $=$ count $-1$;

end

end

endmodule