digital logic design Q$2)$ Design a $2$x$2-$bit signed multiplier. The inputs to the multiplier are two $2-$bit signed $2\text{'}$s complement numbers. $($a$)$ Determine the number of output bits. $($b$)$ Construct the truth table. $($c$)$ For each output, draw the Karnaugh Map and find a simplified expression. $($d$)$ Implement the circuit and reduce the cost by making use of componnents common to each output. Use XOR$/$XNOR gates whenever possible.