Do 3 and4

Question 3 - Verilog- (12 Points] Module A Verliog code ts showm blo. input clk input bp; input ld input [2:0] din output [2:01 q reg [2:0] q always o (posedge clk or negedge resetn if (-resetn) q- 3b011 else if (ld) q din; else if (bp) else -q 1 Read each of the following statements carefully. If the entire statement is true in relation to Module_A, circle T (True) otherwise circle F (False). T F Module A is a(n) up/down Counter TF 1-bit reset_n input is to set the initial value of the module (output) to all zero F Both the reset_n and the Id are synchronous input T Upon reset (reset-n is going from 1 0), on the next positive edge of clock F the output of Module_A, i.e. q, if ld input is low, will change to 100 (3'b100) Question 4 -Verilog - Structural [16 Points]: Draw the circuit diagram corresponding to the given Verilog description. module Question4 (X, Y); inputf4:0] X; output Y wire[2:0] N; not NI (Y, N[2]); and NAI (N[2], N(I), X[2], N[OD; r NOI (N[O), X[O), X[ID. NO2 (N[I], X[3], X(4); module