Draw a carry save adder tree using $3$:$2$ counters $($i$.$e$..$ full adders$)$ are building blocks $($wallace tree$)$ to accumulate partial products in the multiplication of two operands in the two complement format, where each operand is $15$ bit long. Assume that radix$-4$ Booth recoding is used. How many levels are there in the tree?, what is the length of the final CPA$($in terms of the number of digit positions across which the carry needs to propagate?, Let the delay of each$-$ level be triangle $3$:$2.$ then what is the total delay required by the tree to reduce the summation of partial products down to two operand, $($excluding the delay of booth$-$recoding$)?,$ Now draw another tree based on the $(4,2)$ compressors. What is the length of final carry$-$ propagate adder? Let the delay of each level be triangle $1$:$2.$ Then what is the total delay of the tree? Derive conditions relating triangle $3$:$2$ and triangle $4$:$2$ under which $($a$)$ The wallace Tree is faster and $($b$)$ The $4$:$2$ compressor tree is faster