Draw the circuit diagram for problem $1$ AND $2$ using only NAND gates. You must not use any OR$,$ NOT, or AND gates. All used NAND gates should have only $2$ input pins. We practice this because the benefit of using only NAND gates is that we only need to buy one type of gate, and it is plausible to increase our gate$-$use efficiency for each IC$.$

$A^{\text{'}}{B}^{\text{'}}+B^{\text{'}}{D}^{\text{'}}+A^{\text{'}}CD$

$A^{\text{'}}D+B^{\text{'}}{D}^{\text{'}}$