Draw the logic block diagram for a memory with $8$ K words of data, where each word is $16$ bits. The memory accesses the data in chunks of one word $($i$.$e$.,$ for each read or write, one word of data is read out or written in$,$ respectively$).$ Show the optimum size for the memory array, the number of address anddata lines required, and any supporting logic blocks $($e$.$g$.,$ see Fig. $11-12$ in your textbook$).$

In the READ mode, the write enable input, $\frac{?}{\text{b}\text{a}\text{r}}(WE),$ is HIGH and the output enable, $\frac{?}{\text{b}\text{a}\text{r}}(OE),$ is LOW. The input tri$-$state buffers are disabled by gate $G_1,$ and the column output tri$-$state

$128$ columns

Eight output tri$-$state buffers

$($a$)$ Memory array configuration

$($b$)$ Memory block diagram

FIGURE $11-12$ Basic organization of an asynchronous $32k8$ SRAM,