Draw the state diagram and state table for a state machine that has a two-bit input in[1:0] and an output out. Consider the initial state to be one where out = 0. In this state machine, all output changes should occur in synch with the clock.

The output should only change in response to the following input sequences. Each two-bit value represents an input condition that along with a clock trigger causes a state change. As indicated above, the output should only change on the clock trigger following the second two-bit value in the sequence.

The clocked input sequence ins[1:0] = 10, 00 causes the output to become 0.

The clocked input sequence ins[1:0] = 01, 00 causes the output to become 1.

The clocked input sequence ins[1:0] = 11, 00 causes the output to toggle (complement) its value.

Assume that your implementation uses an asynchronous active-high INIT to send the state machine to its initial state from any state when the INIT is asserted.

Demonstrate using the partitioning method that your state table contains the minimal number of states, or use it to derive the minimal state table if your original model is not already minimal.