Draw the timing diagram for 3- bit right register to store 3-bit data 111. Considering the positive edge triggering for the output. Mention how many clock cycles are required for storing 3-bit data in this register.

Hint: Use one full clock cycle each time

Question 3. [ 2 marks] Draw the timing diagram for 3- bit right register to store 3-bit data "111". Considering the positive edge triggering for the output. Mention how many clock cycles are required for storing 3-bit data in this register. Hint: Use one full clock cycle each time One clock cycle