ELEC $2220$ Homework #$4$

Due Wednesday, $8/26/2024$

$($Refer to Textbook Chapter $2$ and Digital Logic Circuits Textbook Chapter $1)$

$1.$ A certain CPU uses two$$s complement arithmetic to perform addition of two $8-$bit

signed numbers. Describe what the following condition flags tell you about the $8-$

bit result of this addition. $(1/2$ point each$)$

a$.$ Z $($zero flag$)$

b$.$ N $($sign flag$)$

c$.$ C $($carry flag$)$

d$.$ V $($overflow flag$)$

$2.$ Perform the following calculations as they would be done by the $8-$bit CPU of

problem $1.$ Write the hex values in binary to perform the calculation. Show the $8-$

bit result in hexadecimal and the four condition flag values $(1$ point for the result

and $1$ point for the flags$).$

a$.0$xA$8+0$xCA

b$.0$xFE $+0$x$02$

c$.0$x$550$x$73$

d$.0$x$900$x$09$