Electronic Pool Filler Project Summary

Read this entire specification carefully. Like a specification you will receive in industry, the

information is spread out and not necessarily organized as you might expect. An important item

might be buried in the middle of a paragraph where it is not expected. As you are responsible for

meeting all the requirements, read this document slowly and carefully!

The current method for maintaining the water level in a swimming pool is to connect a float to a

valve. If the float is below a certain level, then the valve opens and water flows into the pool. Our

company has won a contract to create an electronic pool filler that has two speeds. This specification

details the requirements for the controller circuit.

There are two inputs and two outputs:

Inputs:

L: $1$ means the pool level is low and should fill slowly; $0$ means pool level is normal

V : $1$ means the pool level is very low and should fill quickly; $0$ means fast fill is not needed

Outputs:

R: $0$ means slow fill valve should be off; $1$ means the slow fill valve should allow water flow

F: $0$ means fast fill valve should be off; $1$ means the fast fill valve should allow water flow

There are rules that must be followed:

F may be asserted for no more than $2$ clocks and may not assert again until V$=0$ for at least

one clock.

The design must have a minimum of $5$ states.

There are some items that are not specified. For example, what should be done if both L and V are $1?$

Can V be asserted for less than $2$ clocks? What if V is asserted for more than $2$ clocks? During which

states can V and F assert or negate?

Come up with ideas on how you'd like to design the system. Interview three different stake

holders to discuss your ideas. Stake holders may be other students, TAs, UGTAs, or family

members. Be sure to document the names of the people you interview and their role. $($That is$,$

their role as student, TA$,$ UGTA, family member, etc.$)$

Once you go through this customer discovery, create two finite state machine designs applying

what you learned from your interviews and using different assumptions. This means

documenting the assumptions made for each design and going through the design process $($State

Definition Table, State Transition Diagram, State Transition Table, Combinational Logic

Design$).$ Note that the two designs you create must be functionally different. That is$,$ you can't

create the same design once as a Mealy machine and once as a Moore machine. That is$,$ the

assumptions you make must be different for the two designs. In addition, at least one of the

designs must be based on Karnaugh maps and logic gates. You will also need to incorporate

flin$-$flons with asvnchronous set and reset. What i need you to do: Task C$-2$: Document the Synchronous Sequential Machines

Design #$1$:$(2$ pts$)$ What assumptions did you make in the design of this machine?

$$

$(3$ pts$)$ Create a state definition table here that describes in plain English what each state in your machine means and what binary values you have assigned to represent each state, inputs, and outputs.

$$

$(12$ pts$)$ Show your state diagrams, state transition tables and your circuit planning work $($Karnaugh maps$/$equations$/$MUX$/$DEC$/$etc$.)$ used in your design process. $($You can do this by hand if you wish, do not show the full circuit schematic here.$)$

$$

$(3$ pts$)$ List your final design equations and required logic gates $($including types of Flip Flops$)$ needed to complete this circuit.

$$

Design #$2$:$(2$ pts$)$ What assumptions did you make in the design of this machine?

$$

$(3$ pts$)$ Create a state definition table here that describes in plain English what each state in your machine means and what binary values you have assigned to represent each state.

$$

$(12$ pts$)$ Show your state diagrams, state transition tables and your circuit planning work $($Karnaugh maps$/$equations$/$MUX$/$DEC$/$etc$.)$ used in your design process. $($You can do this by hand if you wish, do not show the full circuit schematic here.$)$

$$

$(3$ pts$)$ List your final design equations and required logic gates $($including types of Flip Flops$)$ needed to complete this circuit. You might need $5-$variable K$-$maps to finish this project completely Please do each step Thank you so much