Question: Enter the RISC - V instructions shown below into the Editor window. When you are finished, use the Simulator window to assemble your program using

Enter the RISC-V instructions shown below into the Editor window. When you are finished, use the Simulator window to assemble your program using the 'Assemble from Editor' button. Using the simulator, step through each instruction in the program
a. record the machine code for each instruction.
b. note the type (i.e. R-type, I-type, etc) of the instruction
c. show how the machine code bits correspond to the instruction type format presented in class
addi x1,x0,31
addi x2,x0,-5
add x3,x1,x2
slli x4,x3,2
addi x5,x0,100
swx4,0(x5)
lwx6,0(x5)
d. In your report, instruction-by-instruction (in a manner similar to the Module 7 notes), convert the machine code from a hexadecimal number to a 32-bit binary word and show how the bits correspond to the instruction type format presented in class. For example, show how the bits correspond to source and destination registers. Show where the offset bits are for sw and lw instruction. Show where the op code in the instruction bits, etc.
This assignment refers to the circuit diagram on the next page. This circuit is an example of a 'Linear Feedback Shift Register' (LFSR) which has the ability to generate pseudo-random numbers. Each 01 transition in the CLK signal will generate a new random number.
(25%) Using CircuitVerse, create the LSFR circuit.
a. After creating the circuit, make sure to initialize the circuit by toggling the 'preset_02' and 'reset' input.
i. Note: The 'splitter' can be found in the 'Misc' tab and should be created as follows:
Enter Bit Width: 16
Enter bit split: 1111111111111111
b. You can control the CLK input by toggling the 'clk_enable' input.
c. Make a list of the first 10 numbers generated by the circuit.
d. Hand in your list of numbers in both binary and hexadecimal format.
(75%) Export the Verilog code for this circuit using the 'Export Verilog' feature in the Tools tab.
a. Both the testbench code and the Verilog circuit code should be contained within the file that you download.
b. Separate out the design file and the testbench file so you can simulate the circuit using the EDA playground.
c. You will need to edit the testbench and write code to toggle the reset and preset and enable the clock.
d. You will need to edit the design file so that the DD flipflop works the same as it does in CircuitVerse (code to use the 'preset_023' signal must be integrated into the 'reset' if statement).
e. Run a simulation to generate 10 numbers
f. Hand in your list of numbers in both binary and hexadecimal format.
g. Hand in a timing diagram of your simulation
(Extra credit) Design and use CircuitVerse to simulate a circuit that will use the LFSR to encrypt and decrypt a 16-bit message using a one-time pad.
Enter the RISC - V instructions shown below into

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