Examine the principles and techniques used in implementing a processor

Lets look at how pipelined execute can be affected by resource hazards, control hazards and instruction set architecture. Looking at the following fragment of code: ADD X5, X2, x1 LDUR X3, [X5, #4] LDUR X2, [X2, #0] ORR X3, X5, X3 STUR X3 [X5, #0]

What would be the total execution time of the sequence in the 5-stage pipeline that only has one memory? Explain your answer.

Change the code to accommodate the changed ISA. What is the speedup achieved in this instruction sequence? Explain your answer.

Show a pipeline execution diagram for these series of instructions (both initial and end) result.

Answer the questions according to the example above

Please make copy paste available