Exercise 1: (12 pts) How many memory chips are required to construct 8M X 32 memory using 512K X 8 chip? A 2M x 32 memory uses coincident decoding by splitting the internal decoder to row-selection and column-selection. Determine the row and column lines enabled when the input address is (4328)10 A 256K X 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select, (a) Assuming that the RAM cell array is square, what is the size of each decoder, and how many AND gates are required for decoding an address