Exercise $1$ The following system specification with $4$ tasks T$1,...,$ T$4$ is given: The tasks can be executed on different hardware units. The following table shows these units and the according costs and execution times. exec. time $($ms$)$ unit cost $/$unit T$1$ T$2$ T$3$ T$4$ MIPS $20052$ DSP $12020185$ FPGA $2401210$ ASIC $400($a$)$ Assume that every hardware unit can be used at most $1$ time. Note the design space by listing all possible Design Points. A design point is a set of allocation, binding and scheduling $($b$)$ Determine the costs and the execution times of all design points. $($c$)$ Draw the design point to a cost $/$ execution$-$time diagram and mark the Pareto Points. $($d$)$ Are there new design points, if each hardware unit can be used more than just $1$ time? $($e$)$ How many design points exist at least, if a task graph with a tasks is arbitrary mapped to a system with at least $3$ hardware units?