Exercise 2.9 Partition the RTL level design given in Figure 2.25 into two or three modules for better synthesis result. Write RTL Verilog code for the design. For the combinational cloud, write an empty function or a task to implement the interfaces. Exercise 2.10 Design architecture, and implement it in RTL Verilog to realize the following difference equation: y[n]=x[n]x[n1]+x[n2]+x[n3]+0.5y[n1]+0.25y[n2]. Implement multiplication with 0.5 and 0.25 by shift operations. Digital Design of Signal Processing Systems Figure 2.25 Digital design with combinational clouds for different design objectives