Exercise $4.[10$ Marks$]$ Consider a multi$-$core processor with $2$ cores, named $P1$ and $P2.$

Each core has a dedicated cache with the following characteristics:

$2-$way set associative and a $16-$byte capacity;

is initially empty;

follows the MESI snooping protocol;

follows write$-$back and write$-$allocate protocols; and

follows a pseudo$-$LRU replacement policy where

$($i$)$ empty cache lines in a set are filled first, then,

$($ii$)$ if there are any invalid cache lines in a set replace them, then,

$($iii$)$ if no invalid cache lines are present, follows a typical LRU replacement policy.

Given the following list of serialized memory byte address accesses by the cores, determine:

$($a$)$ whether each access results in a cache hit, cold miss, conflict miss, capacity miss, true

share miss, or false share miss;

$($b$)$ the data stored in each cache after all addresses in the list have been accessed; and

$($c$)$ the MESI state of each cache block after all addresses in the list have been accessed.

To answer part $($a$)$ use the above table. To answer parts $($b$)$ and $($c$),$ use the below tables.