Exercise: FUNCTIONS, PACKAGES, AND OVERLOADING For some applications in VHDL, it becomes necessary for the designers to create their own functions and package libraries. In this laboratory, we will try to implement our own package, containing functions that we create. 1) Declare a package name, such as my-package". In the package body, perform the following steps. Note: Assume maximum width of 32 bits 2) Write a function to convert a "bit vector" into an "integer". The function should receive an input of "bit vector" type and return an output of "integer" type 3) It is also necessary to perform the reverse operation. Write a function that converts an input of"integer" type to an output of "bit vector" type 4) Overload the + operation for the following types of additions a) bit vector bit vector= bit vector b) bit vector integer-bit vector 5) Use the package that you created to design a 4-bit counter entity with the following ports and properties PORT(S clk, rst, pst, load Data Count DIRECTION In In Buffer TYPE Bit bit vector (3 downto 0 bit vector (3 downto 0 The counter functions under the following priority 1. When "rst" is enabled, the output is cleared to all zeros 2. When "pst" is enabled, the output is set to all ones 3. Otherwise, on the active edge of the clock a) If load" is enabled-the value of the input from "data" will be loaded into the counter b) If"load" is disabled - the count will increment by 3 Hint: Use your functions to add an integer 3 to the bit vector value