explain the architecture attachedVERMA et al$.$: EFFICIENT SCALING$-$FREE FOLDED HYPERBOLIC CORDIC DESIGN

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$$ using XOR gate. $($b$)$ Shift unit of cosh for Stage $1$ performs iteration $i=1.($c$)$ Shift unit of sinh for Stage $1$ performs iteration $i=1.($d$)$ Logic circuit of computation of output $x_1.($e$)$ Logic circuit of computation of output $Y_1.($f$)$ Logic circuit of computation of output ${}_1.$ The structure of sinh and cosh shift units depends on the expressions of $sinh$ and cosh shown in columns $3$ and $6$ of the second row of Table II$,$ respectively, for iteration $i=1.$