Question: Explain what would happen when you tested your BCD to 7 - Segment Display Decoder on the FPGA board if we replaced the Verilog statement

Explain what would happen when you tested your BCD to 7-Segment Display Decoder on the FPGA board if we
replaced the Verilog statement assign enable =4b1110 with assign enable =4b0111 in display.v?

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