F 1. (50 marks) Consider the 8-to-1 multiplexer shown on the right below. Out of the following, what best describes its function? Data A. decoder 1. B. selector c. distributor D. filter ii) What is used to choose one of the data lines? MUX Y A. S., S, S2 B. Tosh....hy C. data output D. k-maps S,S,S, iii) Implementing F(A, B,C) = {(1,3,4,7) with this MUX, what is fed to 12 ? A. S2 B. 2 C. 1 D.0 Implementing F(A,B,C,D) = (1,3,4,11,12,13,14,15) with this MUX, what is fed to 12 ? A. 0 B. 1 c. D' D. C' v) Implementing F(A,B,C,D) = (1,3,4,11,12,13,14,15) with this MUX, what is fed to 1, ? A. 0 B. 1 C. D' D. C' iv) C. iii) 2. (50 marks) Consider the design of a modulo-4 ripple up-counter using only negative-edge triggered J-K flip flops. i) What is the state equation for the J-K flip flop? A Q(t+1) = JQ'(t) + K'Q(t) B. Q(t + 1) = j'Q' (t) + KQ(t) C. Q(t + 1) = TQ'(t) +T'Q(t) D. Q(t + 1) = j'Q(t) + K'Q(t) ii) What is the resulting device if K = J? A. S-R latch B. S-R flip-flop D flip-flop D. T flip-flop What is the minimum number of flip-flops required for this counter? A 4 B. 3 c. 2 D. 1 What is the count produced by this circuit on the third clock cycle? A. 1 B. 2 3 D. 4 Consider using this circuit as a down-counter? Let Q. denote the ith flip-flop output. Then where should the count be taken from? A. the complement of Qi, i.e. QL B. the complement of Qi, i.e. Qi, after setting ) = 1 and K = 0 C. Qi with the connection of each Q to the clock of the next device D. Q with the connection of all Qis to an AND gate whose output activates the preset. Nw iv) c. w N v)