$($Figure $7)$ is a conceptual description of Stack. When a push operation is performed, data enters the array, and when a pop operation is performed, data enters the array. Inside the actual array is a Stack Pointer, which indicates to which part of the array the data is full, as shown in $($Figure $8).$ In the push operation, after the Stack Pointer increases by $1,$ the input data enters the position indicated by the Stack Pointer, and in the Pop operation, the position indicated by the Stack Pointer appears as output data, and the Stack Pointer decreases by $1.($Figure $9)$ is the input$/$output and main signal of the Stack that can store eight $8-$bit data. Complete the Verilog HDL of $($Figure $9)$ with reference to $($Figure $7)$ and $($Figure $8).$

$($Figure y$)$

module stack $($stack$\_$empty, stack$\_$full, data$\_$out, clk$,$ reset, enable, push$\_$pop, data$\_$in$)$; output stack$\_$empty, stack$\_$full; $//$ If array is empty, stack$\_$empty $=1,$ if array is empty, stack$\_$full $=1$ output $[7$:$0]$ data$\_$out; input clk;

input reset; $//$ reset $=1$ indicates array and stack$\_$pointer $=0$

input enable; $//$ If reset $=0$ and enable $=1,$ push or pop, or no action

input push$\_$pop; $//$ push$\_$pop $=1$ push, $0$ pop

input $[7$:$0]$ data$\_$in;

reg $[7$:$0]$ stack$\_$array$[7$:$0]$; $//$ Store $8$ bits of data

reg $[2$:$0]$ stack$\_$pointer;