Figure Q6 shows a functional block diagram of a custom processor and the Register Transfer Level...

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Figure Q6 shows a functional block diagram of a custom processor and the Register Transfer Level (RTL) codes to perform one of the processor operations. Assume that signal p and q are never '1' simultaneously. The ALU operation is given in Table Q6. SO: ( ) /R12; S1: (p) /R2 R1; R1 R2 (p) /R2 R1; S2: (p) / R1 R1 + R2; (pq) /R20; S3: (p) /R2 <2R1; (q) /R2R1 R2; ( ) / done = 1; A ALU_op B ( ) / goto SO; Figure Q6 Activate Go to Settin ALUop [1:0] 00 01 10 11 Table Q6 Operation A+B A-B Complement B Pass B (a) Derive the RTL-CS (control sequence) table for the controller to implement the operation as described. (b) Draw the functional block diagram of the controller. (c) Consider the situation if, in state S3 of the control sequence, signal p and q are allowed to be '1' simultaneously. What will be the problem? Suggest how would you overcome this problem. Figure Q6 shows a functional block diagram of a custom processor and the Register Transfer Level (RTL) codes to perform one of the processor operations. Assume that signal p and q are never '1' simultaneously. The ALU operation is given in Table Q6. SO: ( ) /R12; S1: (p) /R2 R1; R1 R2 (p) /R2 R1; S2: (p) / R1 R1 + R2; (pq) /R20; S3: (p) /R2 <2R1; (q) /R2R1 R2; ( ) / done = 1; A ALU_op B ( ) / goto SO; Figure Q6 Activate Go to Settin Figure Q6 shows a functional block diagram of a custom processor and the Register Transfer Level (RTL) codes to perform one of the processor operations. Assume that signal p and q are never '1' simultaneously. The ALU operation is given in Table Q6. SO: ( ) /R12; S1: (p) /R2 R1; R1 R2 (p) /R2 R1; S2: (p) / R1 R1 + R2; (pq) /R20; S3: (p) /R2 <2R1; (q) /R2R1 R2; ( ) / done = 1; A ALU_op B ( ) / goto SO; Figure Q6 Activate Go to Settin ALUop [1:0] 00 01 10 11 Table Q6 Operation A+B A-B Complement B Pass B (a) Derive the RTL-CS (control sequence) table for the controller to implement the operation as described. (b) Draw the functional block diagram of the controller. (c) Consider the situation if, in state S3 of the control sequence, signal p and q are allowed to be '1' simultaneously. What will be the problem? Suggest how would you overcome this problem. Figure Q6 shows a functional block diagram of a custom processor and the Register Transfer Level (RTL) codes to perform one of the processor operations. Assume that signal p and q are never '1' simultaneously. The ALU operation is given in Table Q6. SO: ( ) /R12; S1: (p) /R2 R1; R1 R2 (p) /R2 R1; S2: (p) / R1 R1 + R2; (pq) /R20; S3: (p) /R2 <2R1; (q) /R2R1 R2; ( ) / done = 1; A ALU_op B ( ) / goto SO; Figure Q6 Activate Go to Settin