Fill in the simple 5-stage pipeline chart for the code sequence and use forwarding whenever possible. Draw an arrow to indicate where forwarding occurs. Assume the machine:

allows a register to read and write in the same clock cycle (i.e. WB and ID can be performed in the same cycle)

has no cache misses.

Clock Cycle 3 4 1 2 5 6 17 8 9 10 Instruction ADDWI R1, R2, #1 ADDW R4, R1, R3 SW R1, 0 (R2)