Fill the following table for the cache hierarchy described, using the definition terminology used in class and the notes. A $256$KiB L$2$ cache is $8-$way associative with $64$B block size. It is part of a $32-$bit architecture.

Note: An answer to a question involving bit cannot be a $4$ or $5$; you must include the unit i$.$e$.$ a $4$bit or $5$bit would be not only appropriate but possibly correct.

$(1)$ A $($associativity$)=8$ filled for you

$(2)$ C $($number of lines$)=$

$4096$

$(3)$ K $($block length$)=64$ filled for you

$(4)$ Number of bit for a line offset$/$index $=$

$12$ bits

$(5)$ Number of bit for a block offset$/$index$=$

$12$ bits

$(6)$ T num of bit of tag $=$

$17$ bits

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