Find the CMOS switch model networks for a $3-$input NOR gate

Connect the register of the figure below including a $4$ x $1$ MUX and three D$-$FFs so that it will operate synchronously according to the following function table, using mode selection inputs S$1$ and S$0$

$\backslash$table$[[S_1,S_0,$Register Operation$],[0,0,$No change$],[0,1,$Load parallel data$],[1,0,$Shift up$],[1,1,$Clear register to $0]]$

$D_i-$

Clock