First turn $317$ into a $10$ bit binary code and then make a moore machine state diagram and state table then get Q$1+,$Q$2+.$Q$3+$ and Z and make a circuit

$2.$ Sequence Detector Design

The Moore $($or synchronous$)$ sequence detector circuit has the inputs $x,Rx,CLK$ and the output Z as shown in Figure $1.$

Figure $1$: Port description of sequence detector

When the Rx signal goes from $"0"$ to $"1",$ the sequence detector is operational, and the input X is ready to receive a binary signal. When $Rx=\text{'}0\text{'},$ the circuit resets and the output Z is $"0".$ The output Z goes to $"1"$ when X receives the input sequence of $"x_3{x}_2{x}_1{x}_0",$ where $"x_0"$ is the first bit of the sequence, followed by$"x_1"$ at the next clock cycle and so on$.$ The output Z will hold its value of $"1"$ until X receives a second sequence of $"Y_3{Y}_2{Y}_1{Y}_0",$ to make the output Z go to $"0".$ Once again, $"Y_0"$ is the first bit of the sequence, followed by$"Y_1"$ at the next clock cycle and so on$.$ For all the other inputs of $x$ the output Z will hold its value. The sequences $"x_3{x}_2{x}_1{x}_0"$ and $"Y_3{Y}_2{Y}_1{Y}_0"$ are determined by using the last three digits of your student number to form a decimal number ranging from $0$ to $999.$ Converting this decimal number to binary yields a maximum of $10$ bits $("Z_1{Z}_0{Y}_3{Y}_2{Y}_1{Y}_0{x}_3{x}_2{x}_1{x}_0")$ where $"x_0"$ is the least significant bit and $"Z_1"$ is the most significant bit. Let the first four least significant bits be used for $"x_3{x}_2{x}_1{x}_0"$ and let the next four bits be used for $"Y_3{Y}_2{Y}_1{Y}_0".$ Bits $"Z_1{Z}_0"$ can be ignored. If any of thesequences for $"x_3{x}_2{x}_1{x}_0"$ and $"Y_3{Y}_2{Y}_1{Y}_0"$ are $"0000"$ then change the sequence to $"0001"$ and if any of the sequences are $"1111"$ then then change the sequence to $"0111".$

$3.$ Design Procedure

Develop the state diagram and the state table for the sequence detector circuit while ensuring you are using the fewest number of states. To reduce the number of logic gates of your design, make state assignments using the following guidelines $($see Roth, Fundamental of Logic Design, $5^{th}$ Ed$.[$Thomson Brook$/$Cole$.2004]$ for details$)$:

States which have the same next state for a given input should be given adjacent assignments.

States which are the next states of the same state should be given adjacent assignments.

States which have the same output for a given input should be given adjacent assignments.

Please note that in many cases it is very challenging to make state assignments while satisfying all three conditions. See class notes on the application of the three conditions when making state assignments. In some cases, you can satisfy some of the above conditions at the expense of other conditions. As a result, multiple state assignment solutions can be explored while trying to satisfy as many of the three conditions as possible. Make two different types of state assignments based on the above guidelines while trying to satisfy as many of the three conditions as possible. Derive the truth tables, logic equations and logic circuit using your choice of flip$-$flops for the two state assignments. Determine the cost of each design by counting the number of gates and the number of inputs for each gate as done in the course notes. Select the design with the lower cost and implement the design on Quartus and on the FPGA.

A second option is to make two state assignments based on the grey code sequence. The first state assignment starts at zero and counts forward. For three flip$-$flops the state assignments are $($state $0=000,$ state $1=001,$ state $2=011,$ and so on$).$ The second state assignment starts at zero and counts backward. For three flip$-$flops the state assignments are $($state $0=000,$ state $1=100,$ state $2=101,$ and so on$).$ Note that, when using grey code state assignment, usually only bit changes when going from one state to another thus satisfying these two grey code state$2$ of $4$

Please note that in many cases it is very challenging to make state assignments while satisfying all three conditions. See class notes on the application of the three conditions when making state assignments. In some cases, you can satisfy some of the above conditions at the expense of other conditions. As a result, multiple state assignment solu