fix the errorss on quartus software and complie until successful - verilog code will give thumbs up for correct answer

The code given intentionally has errors. See if you can find them all. You can also find this in design file knight_rider. module knight_rider Input wire CLOCK_50, output wire [9:0) LEDR ); wire slow_clock; reg (3:0) count; reg count_up: clock_divider ue (.fast_clock (CLOCK_50), slow_clock(slow_clock)); always @ (posedge slow_clock) begin if (count_up) count