For a $32-$bit MIPS architecture, a $$bridge$$ called memory$-$bus of $16-$bit wide

transfer data bytes between DRAM memory and CPU. A clock of $8-$MHz is used

for the bus, which is a different and slower clock from the CPU clock due to the

speed gap between CPU execution and data communication between CPU and

memory. The bus clock represents the speed of the bus and refers to how much

data can move across the bus simultaneously by the bus$-$width, such as $16-$bit

in this case. This architecture has