For a four$-$way set associative cache design with a $23-$bit address, the following bits of the address are used to access the cache.

Virtual address: $0010101011101011011011010111000$

TLB

$\backslash$table$[[$Val Dir Ref,Tag,Physical page number$],[1,1,1,00111110111010010111,00111100011010000111],[0,0,0,00101110111010100101,00101110110010100101],[1,0,0,01101010111010110011,01101010111110110001],[1,0,1,00101010111010110111,00000010101010010000],[0,0,0,00101010111010110111,00000010011010011111]]$

$3-1.$ If a CPU request triggers the hit signal from TLB$,$ translate the given virtual address into a physical address

$3-2.$ Assume this CPU has a four$-$way set associative cache with $64$KiB size, and $1,664$ byte address is mapped to $26$ block address.

What are the index and block offset bits of the physical address, calculated from $3-1?$