For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes,...
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For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes, 2-way Set Associative cache. CPU requires to access following memory locations while running a program "Test_Cache". 1024, 137, 11, 75, 74, 72, 133, 7, 69, 130, 129, 66, 65, 10, 5, 3 (for convenience, addresses are given in decimal). Calculate the Hit ratio assuming the cache is empty at the beginning. Also count the number of blocks replaced in cache memory if LRU (least Recently Used) is used as replacement algorithm. Please construct a table as follows and calculate/provide info for each address. 3. Memory Block of Set no Hit/Miss Line Consequence Comments, if any address RAM no For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes, 2-way Set Associative cache. CPU requires to access following memory locations while running a program "Test_Cache". 1024, 137, 11, 75, 74, 72, 133, 7, 69, 130, 129, 66, 65, 10, 5, 3 (for convenience, addresses are given in decimal). Calculate the Hit ratio assuming the cache is empty at the beginning. Also count the number of blocks replaced in cache memory if LRU (least Recently Used) is used as replacement algorithm. Please construct a table as follows and calculate/provide info for each address. 3. Memory Block of Set no Hit/Miss Line Consequence Comments, if any address RAM no
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Vector Mechanics for Engineers Statics and Dynamics
ISBN: 978-0073212227
8th Edition
Authors: Ferdinand Beer, E. Russell Johnston, Jr., Elliot Eisenberg, William Clausen, David Mazurek, Phillip Cornwell
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