For all $2$ parts, assume that before the code block is executed, x$11$ is initialized to $5$ and x$12$ is initialized to $2.$ Other registers, if un$-$initialized can be assumed to be $0.$

$(5$pts$)$ Suppose you executed the code below on a pipelined system that

does not handle data hazards.

Also, the register file is NOT a fast register file, i$.$e$.$ it$$ does not have the feature of reading and writing in the same clock cycle. For example, if the old value of x$1$ is $10.$ Now, let$$s assume that in Clock Cycle $5($CC$5),$ we are both writing a new value of $20$ to x$1$ and also reading x$1$ in the same clock cycle. Then, the output value from the read would be $10,$ NOT $20.$ This new value of $20$ will be available in x$1$ only from the next clock cycle CC$6.$

In this context, what will be the final values of registers x$13,$ x$14,$ and x$15$ at the end of this code block?

I$1$: addi x$13,$ x$11,1$

I$2$: add x$14,$ x$0,$ x$12$

I$3$: sll x$15,$ x$11,$ x$12$

I$4$: sub x$13,$ x$15,$ x$14$

I$5$: add x$14,$ x$15,$ x$13$