for each$)$ Design a sequential circuit that converts a serial stream of bits from Manchester code to NRZ code. Assume that a double frequency clock is

available. If the input changes occur slightly after the clock edge, glitches $($false outputs$)$ might occur to outputs. If possible, assign the don't$-$cares in the output part of your state table to eliminate some of the glitches. Indicate places in the output waveform where glitches $($false outputs$)$ can occur.

$($a$)$ Derive the state graph and table for a Mealy sequential circuit.

$($b$)$ Repeat $($a$)$ for a Moore sequential circuit.

Please answer both questions. Besides, that's all the information I get