For problem $2\mathrm{.}18,$ please use the following data for the direct$-$mapped $($DM$)$ and $4-$way

set associative $(4$WSA$)$ caches:

Hit time:

DM: $0\mathrm{.}86$ nsec running on a $0\mathrm{.}5$ nsec clock $=2$ cycles.

$4$WSA: $1\mathrm{.}37$ nsec running on a $0\mathrm{.}83$ nsec clock $=2$ cycles.

Miss rate: $DM=2\mathrm{.}2\%$;$4$WSA$=0\mathrm{.}33\%$

Miss penalty: DM $=18$ cycles; $4$ WSA $=11$ cycles.

You are investigating the possible benefits of a way$-$

predicting L$1$ cache. Assume that a $64$ KB four$-$way set associative single$-$banked

L$1$ data cache is the cycle time limiter in a system. For an alternative cache orga$-$

nization, you are considering a way$-$predicted cache modeled as a $64KB$ direct$-$

mapped cache with $80\%$ prediction accuracy. Unless stated otherwise, assume that

a mispredicted way access that hits in the cache takes one more cycle. Assume the

miss rates and the miss penalties in question $2\mathrm{.}8$ part $($c$).$

a$.[12]<mn>2</mn><mn>.</mn><mn>3</mn>$: What is the average memory access time of the current cache $($in

cycles$)$ versus the way$-$predicted cache?

b$.[15]<mn>2</mn><mn>.</mn><mn>3</mn>$: If all other components could operate with the faster way$-$predicted

cache cycle time $($including the main memory$),$ what would be the impact on

performance from using the way$-$predicted cache?

c Way$-$predicted caches have usually been used only for instruction

caches that feed an instruction queue or buffer. Imagine that you want to try out

way prediction on a data cache. Assume that you have $80\%$ prediction accuracy

and that subsequent operations $($e$.$g$.,$ data cache access of other instructions,

dependent operations$)$ are issued assuming a correct way prediction. Thus a

way misprediction necessitates a pipe flush and replay trap, which requires

$15$ cycles. Is the change in average memory access time per load instruction

with data cache way prediction positive or negative, and how much is it$?$

d$.[10]<mn>2</mn><mn>.</mn><mn>3</mn>$: As an alternative to way prediction, many large associative L$2$

caches serialize tag and data access so that only the required dataset array

needs to be activated. This saves power but increases the access time. Use

CACTI's detailed web interface for a $0\mathrm{.}065m$ process $1MB$ four$-$way set

associative cache with $64-$byte blocks, $144$ bits read out, $1$ bank, only $1$

read$/$write port, $30$ bit tags, and ITRS$-$HP technology with global wires. What

is the ratio of the access times for serializing tag and data access compared to

parallel access?