Question: For the A/D converter presented in class 6 slides 20 and 21, present the timing diagram and the digital output for a 4.5 volts input

 For the A/D converter presented in class 6 slides 20 and21, present the timing diagram and the digital output for a 4.5

volts input Timing Diagram of an A/D Converter (Vin = 5.59 V)

For the A/D converter presented in class 6 slides 20 and 21, present the timing diagram and the digital output for a 4.5 volts input Timing Diagram of an A/D Converter (Vin = 5.59 V) Clock STRT Data ready (End-of-conversion) Start conversion SAR Reset INTR 11 D . 10 LG 0 DS 10 D4 D 1 22 D DO 10 7.50000 6.2500 DAC VOUT 5.625 5.546875 5.3125 5.0000 5.5859375 5.46875 0.00 Conversion time A/D Converters Analog input VIN- Op amp comparator Clock oscillator INTR (End-of-conversion) WR MSB Successive-approximation register (SAR) LSB DDD Start (Start conversion) DID. Ds De D Enable Jinc 6 Digital output Data-bus liras 4 3 2 1 0 Output buffer VREF=10V 8-bit D/A converter (DAC) DAC Input Vour (a) (b) D, DE D D4 D D) D D. DAC VOUT 5.0000 2.5000 1.2500 0.6250 0.3125 0.15625 0.078125 0.0390625 17 For the A/D converter presented in class 6 slides 20 and 21, present the timing diagram and the digital output for a 4.5 volts input Timing Diagram of an A/D Converter (Vin = 5.59 V) Clock STRT Data ready (End-of-conversion) Start conversion SAR Reset INTR 11 D . 10 LG 0 DS 10 D4 D 1 22 D DO 10 7.50000 6.2500 DAC VOUT 5.625 5.546875 5.3125 5.0000 5.5859375 5.46875 0.00 Conversion time A/D Converters Analog input VIN- Op amp comparator Clock oscillator INTR (End-of-conversion) WR MSB Successive-approximation register (SAR) LSB DDD Start (Start conversion) DID. Ds De D Enable Jinc 6 Digital output Data-bus liras 4 3 2 1 0 Output buffer VREF=10V 8-bit D/A converter (DAC) DAC Input Vour (a) (b) D, DE D D4 D D) D D. DAC VOUT 5.0000 2.5000 1.2500 0.6250 0.3125 0.15625 0.078125 0.0390625 17

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