For the circuit below: $40$pts

a$.$ Draw the timing arcs

b$.$ Write the equations for the timing arcs for both setup and hold and evaluate.

c$.$ Determine the max clock frequency

d$.$ Is hold time met?

e$.$ If hold time is not met fix the problem with $0\mathrm{.}2$ns delay buffers and recalculate the

max clock frequency.

f$.$ What path is the critical path?