For the digital computer specifications and the seven-cycle hardwired control unit designed in the class, answer the following: 1. For the "Add" memory reference instruction (op-code-001 "q) with indirect addressing mode (Tag-100, "m4"): List the cycles this instruction will go through from the start of its fetching to the start of fetching the next instruction in the following two cases: a. 1. Interrupt Condition IC-0, 2. Interrupt Condition IC-1 b. List all micro-operations along with their control functions for each of the above cycles for the two cases. Repeat the above problem for the "LDA" memory reference instruction (op-code-010"q2) with immediate addressing mode (Tag-110,"ms"): 2. For the digital computer specifications and the seven-cycle hardwired control unit designed in the class, answer the following: 1. For the "Add" memory reference instruction (op-code-001 "q) with indirect addressing mode (Tag-100, "m4"): List the cycles this instruction will go through from the start of its fetching to the start of fetching the next instruction in the following two cases: a. 1. Interrupt Condition IC-0, 2. Interrupt Condition IC-1 b. List all micro-operations along with their control functions for each of the above cycles for the two cases. Repeat the above problem for the "LDA" memory reference instruction (op-code-010"q2) with immediate addressing mode (Tag-110,"ms"): 2