For the following datapath and control design: QUA Insn Mem Register File Rwe Rds BR ALLINB...

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For the following datapath and control design: QUA Insn Mem Register File Rwe Rds BR ALLINB Data Mem Rad ALUOP DMwe Control? (a) Why the PC register is increased by 4 not 1? (b) What is the two possible addresses that can be stored in the PC register if the value of BR is equal to 1? (c) Determine the value of control signals if we want to execute lw instruction. Consider a non-overlapped memory system that has two levels of memories. The cache memory has an access time of 100 ns and the RAM memory has an access time of 1200 ns. (a) If the effective access time is 50% greater than the cache access time. What is the hit ratio H? (b) Suppose that we can change the cache design such that we get H equals to 0.9916. Calculate the new effective access time and determine if this change improves the performance or not? For the following datapath and control design: QUA Insn Mem Register File Rwe Rds BR ALLINB Data Mem Rad ALUOP DMwe Control? (a) Why the PC register is increased by 4 not 1? (b) What is the two possible addresses that can be stored in the PC register if the value of BR is equal to 1? (c) Determine the value of control signals if we want to execute lw instruction. Consider a non-overlapped memory system that has two levels of memories. The cache memory has an access time of 100 ns and the RAM memory has an access time of 1200 ns. (a) If the effective access time is 50% greater than the cache access time. What is the hit ratio H? (b) Suppose that we can change the cache design such that we get H equals to 0.9916. Calculate the new effective access time and determine if this change improves the performance or not?

Answer rating: 100% (QA)

a The PC register Program Counter is increased by 4 not 1 because it stores the address of the next instruction to be fetched In most modern computer ... View the full answer