For the following MIB code Loop: Add $7, 1, $3 LW &1, 0(82) Add $5, $1, $3 XOR $6, $L, $5 sw $6, 07) Lw $3,0 (17) Add $10, $10, 4 bne $101 $3, loop Assume the following latencies for each stage & that the above loop itterates times * Compute the execution time when running this code ono- I single cycle MIPS CPU 2. Multiple Cycle MIPs Clu 3. pipelined cpu with for wanding only CALO) & branch resolved in the IDstage initialized to be taken solve by showing R/Ws & the number of stall cycles for each one (Ignore initial pipeline) 4 - pipe lined ofu without any forwarding & the branch resolved show Stall cycles between instructions if exist. Ignore initial pipeline fill cycle s-schedule the MiB code given above by changing instru order to minimize stall cycles when running on the pipelined cpu with assumption in part 3. solve the execation stage on Showing the R/ Ws & the neaber of stall cycles by each one for For the following MIB code Loop: Add $7, 1, $3 LW &1, 0(82) Add $5, $1, $3 XOR $6, $L, $5 sw $6, 07) Lw $3,0 (17) Add $10, $10, 4 bne $101 $3, loop Assume the following latencies for each stage & that the above loop itterates times * Compute the execution time when running this code ono- I single cycle MIPS CPU 2. Multiple Cycle MIPs Clu 3. pipelined cpu with for wanding only CALO) & branch resolved in the IDstage initialized to be taken solve by showing R/Ws & the number of stall cycles for each one (Ignore initial pipeline) 4 - pipe lined ofu without any forwarding & the branch resolved show Stall cycles between instructions if exist. Ignore initial pipeline fill cycle s-schedule the MiB code given above by changing instru order to minimize stall cycles when running on the pipelined cpu with assumption in part 3. solve the execation stage on Showing the R/ Ws & the neaber of stall cycles by each one for