For this problem we will be looking at a $6464$ SRAM $($i$.$e$.,$ each wordline drives $64$ cells, and each bitline has $64$ cells on it$),$ with each cell shown below. The cell's layout is $2m$ tall and $2\mathrm{.}5m$ wide, and both the wordline and bitline wires are $0\mathrm{.}1m$ wide. You can assume that $C_G=C_D=C_S=2f\frac{F}{}m($with a minimum length$),R_{sqn}=10k\frac{}{},R_{sqp}=20k\frac{}{},$ and that for the wordline and bitline wires, $R_w=0\mathrm{.}1\frac{}{}$ and $C_{\text{w}\text{i}\text{r}\text{e}}=0\mathrm{.}2f\frac{F}{}m.$

a$)$ For this SRAM, what is the total capacitance on each wordline $(C_{wL})?$ What is the total capacitance on each bitline $(C_L)?(15$ pt $)$

b$)$ Assuming this SRAM works at $1$ GHz and $V_{DD}=1V,$ how much dynamic power is consumed due to the capacitance of the wordlines $(P_{\text{w}\text{o}\text{r}\text{d}})$ and bitlines $(P_{\text{b}\text{i}\text{t}}?(20$ pt $)$