For this second project, you will proceed with the design and simulation of a four$-$bit

Up$-$Down counter; you will need to use Flip$-$Flops JK negative edge triggered $74112.$

The flip flops are available in $.$mf library. This flip flops come in Dual$-$Packages so all

you need is two of them. Implementation with other class of devices, like $71$LS$161/163$

will not be considered. You need to take into consideration the following parameters:

a$)$ The simulations should use a clock of $25$ MHz$.$

b$)$ The counter must operate with Up$\_$Down, to select the counting direction, clear,

preset and clock inputs and the respective four outputs Qa$,$ Qb$,$ Qc$,$ Qd$.$

c$)$ The snapshots should show a complete count $($from $0000$ to $1111$ and another for

a count from $1111$ to $0000)$ and should show uses of Asynchronous Clear and

Preset.

$4)$ The project will be evaluated considering the following aspects:

a$)$ Result correctness.

b$)$ Report completeness.

c$)$ Clarity of ideas.

d$)$ Bonus points implementing with ALTERA boards DE$2-115.$