FPGAs and Digital Design$/$Advanced Digital System

Design

Question $1$: Understand the merge sort algorithm which can be used to sort $8$ numbers in

ascending order. You are required to design a hardware representation for it using compare and

swap blocks as done in class for bubble sort algorithm.

Question $2$: For the following equations design its equal hardware representation:

acc$0=$acc$1+in1$

acc $1=$acc$0+in2$

out $=$ acc $0+$acc$1$

where in$1$ and in $2$ are two $32-$bit inputs, out is a $40-$bit output, and acco and acc$1$ are two $40-$bit

internal registers.

Question $3$: Design a $3-$bit counter such that counter pattern is $(0,3,6)$ or $(1,4,7)$ or $(2,5)$ using

Boolean logic and basic gates. You should first create a truth table for it$,$ create minterms or

maxterms and then use the SoP or PoS to create your final digital design.

Question $4$: Implement the following Boolean expression using PAL and PLAs $($for a $3$ inputs, $x,y$

and z $).$

$F1={\displaystyle \underset{?}{\overset{?}{}}}m(3,5,7)$ and $F2={\displaystyle \underset{?}{\overset{?}{}}}m(4,5,7)$

Question $5$: Identify the total number of $3-$input $2-$output LUTs that will be used to implement

the following circuit diagram.

$38$ line Decoder Logic Diagram