General Statement: Implement function F(A,B,C,D) = Sum(0,1,7,13,15) +Dont Cares(2,6,8,9,10) by only using two-level logic. Thus, you are to draw the circuit using the Xilinx ISE Schematic Editor, and then simulate it using the Xilinx ISE Simulator. You are to get a printout of the Simulation results (i.e. the timing diagram).

Also you are to provie:

1. Verilog test bench code

Once your design is verified using the Xilinx simulator, you are to get (1) a printout of the actual circuit from the Schematic Editor and (2) a printout of the simulation waveforms.

// Initialize Inputs

integer i=0;

initial begin

D = 0;

C = 0;

B = 0;

A = 0;

#16 $display ("starting test");

for (i=0; i<16; i=i+1)

begin

{A, B, C, D} = i;

#16 $display ("A B C D=%b%b%b%b, {F} = %b", A, B, C, D, F);

end

end

or modify testbench code:

initial begin

// test case 0

A = 0;

B = 0;

#10;// Wait 10 time units

// test case 1

A = 0;

B = 1;

#10;// Wait 10 time units

// test case 2

A = 1;

B = 0;

#10;// Wait 10 time units

// test case 3

A = 1;

B = 1;

#10;// Wait 10 time units

$stop;

end