Give an example of a quiescently consistent register execution that is not regular.

FIGURE 4.22

Boolean to M-valued atomic SRSW register algorithm.

Transcribed Image Text:

public class AtomicSRSWRegister implements Register<1nt> { 2 private static int RANGE = M; 3 boolean[] r_bit = new boolean [RANGE]; // atomic boolean SRSW public AtomicSRSWRegister (int capacity) ( for (int i = 1; i <= RANGE; 1++) r_bit[i] = false; 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 } r_bit [0] = true; } public void write(int x) { r_bit [x] = true; for (int i = x 1; 1>= 0; i--) r_bit[i] = false; } public int read() { for (int i = 0; i <= RANGE; i++) if (r_bit[i]) { return i; } return -1; // impossible public class AtomicSRSWRegister implements Register<1nt> { 2 private static int RANGE = M; 3 boolean[] r_bit = new boolean [RANGE]; // atomic boolean SRSW public AtomicSRSWRegister (int capacity) ( for (int i = 1; i <= RANGE; 1++) r_bit[i] = false; 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 } r_bit [0] = true; } public void write(int x) { r_bit [x] = true; for (int i = x 1; 1>= 0; i--) r_bit[i] = false; } public int read() { for (int i = 0; i <= RANGE; i++) if (r_bit[i]) { return i; } return -1; // impossible

Answer rating: 100% (QA)

This implementation of a register is quiescently consistent because any read operation that starts ... View the full answer