give me the correct and detailed answer for this cache replacement : the question I provided of the High performance computer architecture course as follows in the image :When Cache is full, you need to select a block to replace. There are several

different block replacement schemes, such as FIFO or the oldest block

replacement, random $($select a block to replace randomly$),$ and LRU $($Least

recently used block replacement$).$

In this project, you need to use Verilog $($preferred$),\frac{C}{C}++,$ or python to calculate

and compare efficiency or the Hit Rates of the three aforementioned schemes.

Assume there are $6$ block entries in cache and fully associative structure is used.

You need to use the block reference $log$ in a provided array.

You will need to submit a project report before the due time. You need to follow

the format in The ECE lab report guidance and include an introduction, problem

statement, implementation, result and comparison, conclusion and references.

The block reference log:

int $arra{y}_p$ages $[]=\{,49,50,50,52,30,49,43,49,20,31,$

$26,37,43,43,43,43,43,20,20,30,$

$21,25,25,25,25,25,25,31,20,20,$

$11,11,11,12,12,49,43,50,5020,$

$11,43,50,12,12,49,43,50,50,50$

$\}$;