Give me the direct ans is enough

What device is shown by the following circuit? High Q Clock Ck >Ck Ck K K 0 K K Qo 0, Q2 O, A. Adder B. Ripple counter Shift register D. Synchronous counter How would F = AXB-C be implemented on a zero-address instruction machine? PUSHA PUSH B MUL PUSH C SUB POP F B. PUSHA MULB SUBC POP F C. LOAD A MULB SUBC STORE F D. LOAD A LOAD B MUL LOAD C SUB STORE F If a memory word length is 128 bits, which of the following are possible addresses of successive memory words? 1.0, 16, 32, 48, ... II. O, 128, 256, 384, ... III. 96, 112, 128, 144, ... . IV. 32, 40, 48, 56, ... I only. B. II only. I, and III only. D. IV only